In a typical non-volatile memory device such as electrically erasable programmable read only memories (EEPROM), a charge pump is needed to generate the high internal programming voltage necessary to achieve electron tunneling during programming steps. The charge pump circuit takes in a low voltage input and generates a high voltage output using multiple voltage pumping stages.
FIG. 1 shows a simple charge pump circuit, which is commonly known as a Dickson charge pump. The Dickson charge pump includes a plurality of diode ladder stages 10 wherein complementary charge pump clock signals 18, 20 are provided to successive stages. Each diode ladder stage 10 comprises a diode 12 and a capacitor 14 connected together. The charge pump circuit operates by passing charges along successive stages of the diode ladder 10 using capacitive coupling of the complementary charge pump clock signals 18, 20 that are provided by an oscillator circuit. Since the voltage is not reset after each pumping cycle, the average node potential increases progressively from the input terminal 16 to the output terminal 17 of the diode ladder 10. The maximum output voltage Vmax reached by the Dickson charge pump can be derived from equation (1) below:Vmax=(N+1)×(Vdd−Vt)  (1)where N is the number of diodes 12 in the ladder, Vdd is the supply voltage, and Vt is the threshold voltage of the diodes 12.
The output current Iout provided by the Dickson charge pump can be derived from equation (2) below:Iout=N×C×(Vdd−Vt)×Fosc  (2)where C is the capacitance of capacitors 14, and Fosc is the oscillator output frequency.
These two equations shows the output sensitivity of the Dickson charge pump to the power supply Vdd. As shown in equations (1) and (2), both the maximum voltage output Vmax and the output current Iout decrease with decreasing supply voltage Vdd. Equation (2) also shows that output current Iout is proportional to the oscillator frequency.
FIG. 2 shows a simple ring oscillator that can be used to drive the Dickson charge pump circuit shown in FIG. 1. The ring oscillator is composed of a number of inverter elements 32 connected in a circular manner. An input NAND gate 30 provides a means for disabling the oscillator when a low voltage signal is presented at an ENABLE terminal 28. The oscillator outputs are stable (i.e., φ1=1, φ2=0) when the enable signal 28 is low. When enabled, the input NAND gate 30 inverts the signal from the terminal “A.” The signal is then propagated through the inverters 32 back to point “A.” This process continues until the ENABLE signal 28 goes back to low. The amount of time taken to propagate the signal back to point “A” is determined by the inverter delay. This inverter delay is dependent on the supply voltage Vdd because the supply voltage Vdd is the maximum gate-source voltage that can be applied to the transistors within each inverter stage 32. It is the gate-source voltage that determines the current drive of each inverter stage, which ultimately determines the propagation speed of each inverter stage 32. The signal that is present at point “A” is then provided to a first clock driver portion 24, which is composed of a NAND gate 34, and two inverters 36 connected in a serial manner and generates the φ1 signal 18. The signal that is present at point “B” is provided to a second clock drive portion 26, which is composed of a NAND gate 38 and two inverters 40 connected in a serial manner and generates the φ2 signal 20. The φ1 18 and φ2 20 signals are 180° out of phase with each other.
A drawback of the ring oscillator is that the output frequency φ1 18 and φ2 20 changes with the supply voltage Vdd. More specifically, a lower Vdd causes the oscillator to generate a lower operating frequency output. Together with a lower voltage input level, a charge pump system that employs such an oscillator would generate a relatively weak charge pump output voltage. As a result, the charge pump may fail to provide the desired output current. Therefore, it would be desirable to have an oscillator that is not sensitive to the supply voltage Vdd.
For charge pump systems that supply output voltages to an EEPROM array, a major consideration pertains to leakages through the transistors that are connected to the output voltage terminal Vout 17 (FIG. 1) of the charge pump. There are two main mechanisms for such leakages: the first mechanism is a drain to source current (punch-through) leakage that increases with increasing temperature. The second mechanism is a breakdown leakage that has a threshold that decreases with increasing temperature. FIG. 3 shows the relationship between leakage current 56 and voltage output 58. As shown in FIG. 3, at a low voltage output region 60 (between 0 and 15 volt output), current leakage increases with increasing temperature. In this region, punch-through leakage dominates. However, breakdown leakage occurs at a lower threshold when the temperature is low. For instance, the breakdown occurs at about 15 Volts when the temperature is 25° C. (as denoted by numeral 50) and at about 16 Volts when the temperature is 125° C. (as denoted by numeral 54). Since the programming voltage for EEPROM cells is at about 15.5 volts, when the ambient temperature is at 25° C., the major leakage during programming is due to breakdown leakage. As is shown in FIG. 3, once the breakdown leakage threshold is reached, the leakage current goes up exponentially. As a result, the programming operation of the EEPROM cells may fail, as the charge pump may not be able to keep up with the leakage current.
On the other hand, when the temperature is high, such as 125° C., the breakdown threshold voltage is raised to about 16 V. As a result, the breakdown leakage remains low during the EEPROM cell programming stage. Thus, a charge pump oscillator producing a stable frequency throughout the operating temperature range leads to a heightened programming voltage at high operating temperatures. The drawback of having a heightened programming voltage is that the lifetime of EEPROM cells reduces significantly even with a relatively small increase in programming voltage. For instance, studies have shown that as the temperature rises from 25° C. to 85° C., the endurance of the EEPROM cells is reduced by a factor of three due to the corresponding increase in programming voltage. Therefore, it would be desirable to have a charge pump oscillator that produces an output frequency that is inversely proportional to temperature changes and stable with regard to the supply voltage.